
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:41:15 03/23/2012
-- Design Name:   ALU
-- Module Name:   C:/ProyectosVHDL/PracticaCyclone/ALU/testALU.vhd
-- Project Name:  ALU
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testALU_vhd IS
END testALU_vhd;

ARCHITECTURE behavior OF testALU_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT ALU
	PORT(
		ALUINa : IN std_logic_vector(7 downto 0);
		ALUINb : IN std_logic_vector(7 downto 0);
		NUM_ROT : IN STD_LOGIC_VECTOR (2 downto 0);
		is_Shift : IN std_logic;
		carry_in : IN std_logic;
		opType : IN std_logic_vector(2 downto 0);          
		ALUout : OUT std_logic_vector(7 downto 0);
		flagsOUT : OUT std_logic_vector(1 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL is_Shift :  std_logic := '0';
	SIGNAL carry_in :  std_logic := '0';
	SIGNAL ALUINa :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL ALUINb :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL NUM_ROT : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
	SIGNAL opType :  std_logic_vector(2 downto 0) := (others=>'0');

	--Outputs
	SIGNAL ALUout :  std_logic_vector(7 downto 0);
	SIGNAL flagsOUT :  std_logic_vector(1 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: ALU PORT MAP(
		ALUINa => ALUINa,
		ALUINb => ALUINb,
		NUM_ROT => NUM_ROT,
		is_Shift => is_Shift,
		carry_in => carry_in,
		opType => opType,
		ALUout => ALUout,
		flagsOUT => flagsOUT
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here
		opType <= "000";
		is_Shift <= '1';
		carry_in <= '0';
		ALUINa <= "10001100";
		ALUINb <= "00000001";
		NUM_ROT <= "011";
		wait for 10 ns;
		opType <= "000";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "001";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "010";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "011";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "100";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "101";
		carry_in <= '0';
		wait for 10 ns;
		is_Shift <= '0';
		opType <= "000";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "001";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "010";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "011";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "100";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "101";
		carry_in <= '0';
		wait for 10 ns;
		opType <= "110";
		carry_in <= '0';
		
		wait for 10 ns;

		wait; -- will wait forever
	END PROCESS;

END;
